1. Field of the Invention
The present invention relates to an apparatus and method for implementing flexible redundancy in a divided array architecture scheme. More particularly, the present invention relates to a semiconductor memory device comprising a plurality of memory sub-arrays within the divided array architecture scheme such that the redundancy memory within one of the plurality of memory sub-arrays is usable in any other sub-array.
2. Art Background
In today's semiconductor industry, semiconductor integrated circuit memory devices such as static random access memory (SRAMs), random access memory (RAMs), dynamic random access memory (DRAMs) and the like generally comprise a plurality of memory blocks in the integrated circuit. These memory blocks include a large number of binary elements (i.e., memory cells) for storage of binary data; namely, logic level "ones" and "zeros". The memory cells are arranged in a matrix of rows and columns. Addresses associated with a single memory array access memory locations within the array. Typically, decoding devices are coupled to the memory in order to decode a selected address signal for accessing a desired group of memory cells. The inputs to the array are provided on the wordlines, which usually select the "row"of the address, while the outputs from the array are provided on the bitlines. The bitlines select the "column" of the address.
In the manufacture of such memory arrays, processing defects often randomly occur within the memory chip. In most instances, these memory chips are fully functional except for a single or a small number of rows or columns containing defective memory cell(s). In order to prevent unnecessary scrapping of the chip for having a small number of defects, defect tolerant memory devices have been devised in which redundancy memory is substituted for a selected row and/or column of defective memory.
For many years, redundancy memory had been used strictly for single memory arrays. At that time, semiconductor memory manufacturers had designed and fabricated semiconductor memory devices with a single memory array 1 divided into a plurality of memory blocks 2a-2n as shown in FIG. 1. These memory blocks 2a-2n include at least one block of redundancy memory 2n. Reading data from and writing data into a desired group of memory cells 3 along a local wordline 4 was accomplished by activating the group of memory cells 3 through decoding. The decoding was accomplished in two steps. First, a physical address of a desired memory block containing the group of memory cells 3 is inputted into decoding logic 5 which, in turn, activates the memory block containing the desired group of memory cells 3. As an example, for illustrative purposes, the desired memory block is a first memory block 2a of the plurality of memory blocks 2a-2n. Concurrently therewith, using the same decoding procedure with respect to decoding logic 7, a set of global wordlines 6a-6n including the local wordline 4 is activated, which results in the group of memory cells 3 becoming accessible.
If any block of memory within the single memory array 1 becomes defective, a block of redundancy memory 2n is directly mapped into the physical address of the defective memory block in order to replace the defective memory block. However, such architecture was extremely slow because it required longer read and write signal lines (not shown) between each block in the array and the redundancy memory which, in turn, causes greater read access time delays.
In order to overcome speed limitations associated with the single memory array architecture, semiconductor memory manufacturers began to design and fabricate divided array memory architectures. An example of such architecture is illustrated in FIG. 2, wherein the memory array 10 is divided into four identical sub-arrays 11-14, each of which having eight blocks of memory 11a-11h through 14a-14h and one block of redundancy memory block 11i-14i. The sub-arrays 11-14 are addressed by conventional decoding logic 18 which is coupled to each of the sub-arrays 11-14 through decoding signal lines 20-28. More specifically, the decoding signal lines 20-28 are respectively coupled to every memory block 11a-14i within the sub-arrays 11-14, including all the redundancy memory blocks 11i-14i. Although FIG. 2 shows a specific example, it is apparent that the memory array 10 could be divided into any number of sub-arrays or memory blocks.
In conventional divided array architecture scheme, each block in the memory sub-arrays shares a common physical address with at least one other block in another sub-array. For example, a first block 11a of a first memory sub-array 11 may have the same physical address as a first block 12a-14a of a second, third and fourth memory sub-arrays 12-14 respectively, a second block 11b of a first memory sub-array 11 may have the same physical address as second blocks 12b-14b of other sub-arrays 12-14 and so on.
Although a memory block in each sub-array 11-14 is activated at any one time, only one group of memory cells 16 is accessed. This is due to the fact that each of the memory sub-arrays 11-14 is coupled to an uniquely addressed set of global wordlines 15a-15n, which is decoded by conventional decoding logic 19. The combination of activating both the memory blocks 11-14 and the unique global wordline 15a-15n, where "n" is equal to any whole number, enables access to the desired group of memory cells 16 along a local wordline 17. As shown in FIG. 2, the local wordline 17 is a subsection of the global wordline 15a within the activated memory block 11a. The operation of conventional divided array architectures may be better explained through an example.
If access to certain memory cells in a first block 11a of a first sub-array 11 is desired, the address of the desired block would be decoded by the decoding logic 18 and as a result, four blocks 11a, 12a, 13a and 14a (one for each sub-array) would be accessed because they share an identical physical address. However, since the global wordlines 15a-15n are uniquely addressed, only one wordline, namely wordline 15a, would be activated and thereby allowing the group of memory cells 16, within the first memory block 11a and along the local wordline 17, to be accessed.
An advantage of the conventional divided array architecture over the single array architecture is better overall system performance through quicker memory access time because the read and write signals (not shown) of a divided memory array 10 have to propagate a shorter distance than those in the single memory array 1. However, a disadvantage associated with the divided array architecture is that it is not as flexible as the single array architecture because the redundancy memory blocks 11i-14i are divided so as to support only its corresponding memory sub-arrays 11-14. As a result, redundancy memory stored in one of the plurality of memory sub-arrays cannot be used in any other memory sub-array. In the embodiment in FIG. 2, redundancy memory 11i from a first memory sub-array 11 could not be used in memory sub-arrays 12-14 and so on.
The present invention incorporates a divided array architecture as illustrated in FIG. 2 to enhance system performance by decreasing memory access time, but also preserves flexibility associated with unrestricted use of redundancy memory as in the single array architecture shown in FIG. 1. Based on the foregoing, it would be desirable to have flexible redundancy memory in a divided array architecture. Therefore, it is an object of the present invention to provide an apparatus and method for implementing a plurality of memory sub-arrays within a divided array architecture scheme such that redundancy memory within one of the plurality of memory sub-arrays is usable by any other sub-array.
Accordingly, it is another object of the present invention to provide an apparatus and method for repairing defective memory blocks by mapping redundancy blocks into a physical address of the defective memory blocks.
Another object of the present invention is to provide an apparatus and method to increase a yield of functional memory semiconductor devices.
Yet, it is another object of the present invention is to provide an apparatus and method for allowing :memory sub-arrays within a divided array architecture to use redundancy memory interchangeably.